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Senior Silicon Design Verification Engineer

Google· New Taipei, Banqiao District, New Taipei City, Taiwan
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New Taipei, Banqiao District, New Taipei City, TaiwanFull-timePosted 1w ago

About the role

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Responsibilities

  • Plan the verification of complex digital design blocks by thoroughly understanding architectural specifications and collaborating closely with Design/Architecture teams to map out critical verification scenarios and edge cases.
  • Architect, implement, and enhance scalable constrained-random verification environments using SystemVerilog and UVM, or execute formal verification strategies using SystemVerilog Assertions (SVA) and industry-leading formal tools.
  • Drive root-cause debugging of failed tests alongside RTL Design Engineers to ensure functional correctness and high reliability prior to tape-out.
  • Define and manage functional and code coverage models, drive coverage closure workflows, and identify architectural holes to ensure tape-out readiness.
  • Lead verification sub-initiatives across block and system levels while mentoring junior DV engineers to support team execution.

Qualifications

  • Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
  • 8 years of experience in silicon digital design implementation or verification.
  • Experience verifying digital logic at RTL using SystemVerilog for ASICs.
  • Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
  • Experience with object-oriented programming.

Skills

Required:SystemVerilogUVM (Universal Verification Methodology)Object-oriented programming
Nice to have:SystemVerilog Assertions (SVA)Formal verification
Last updated Oct 23, 2026. Interested? Apply on the company site.

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