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Principal Silicon Product Engineer

Google· Technical Infrastructure
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Sunnyvale, CA, USA$281k - $391kFull-timePosted 1w ago

About the role

Senior-level technical leadership role responsible for serving as the principal technical authority for the Silicon Sourcing organization, bridging hardware engineering design, manufacturing ecosystems, and strategic sourcing across the full silicon lifecycle for Custom Silicon and Off-the-Shelf products.

Responsibilities

  • Serve as the principal technical authority across Custom Silicon (TPUs, gSOCs, ASICs) and OTS products (Switches, PCIe, CXL, CPUs), evaluating vendor technical capabilities, architectural trade-offs, node roadmaps, and manufacturability.
  • Work with engineering to conduct rigorous technical evaluations of leading-edge process nodes (sub-2nm, GAA/RibbonFET, backside power delivery) and specialized nodes. Partner with Tier-1 foundries to assess defect densities, DFM/PDK compliance, and process window margins to secure optimal node execution.
  • Architect and qualify heterogeneous integration paths (CoWoS, InFO, 3D stacking, HBM integration) and sub-tier components (substrates, thermal interface materials), establishing stringent mechanical and thermal readiness gates (e.g., mTV/eTV stress testing).
  • Engage with CTOs, VP-level engineering leaders, and technical teams at Tier-1 foundries and major merchant silicon vendors; define should-cost foundations and de-risk advanced packaging and yield/test parameters to optimize Total Cost of Ownership (TCO).

Qualifications

  • 15 years of relevant experience in Semiconductor Product Engineering, Silicon Architecture, Foundry Engineering, or Technical Sourcing Engineering.
  • Experience with semiconductor product lifecycle: design tape-out, wafer fab processing, parametric yield analysis, advanced packaging/assembly, and high-volume test engineering (ATE/SLT).
  • Experience evaluating and scaling leading-edge nodes (3nm, 2nm, and beyond) and heterogeneous packaging technologies (2.5D/3D, CoWoS, chiplets, HBM).
  • Experience covering both Custom ASIC/COT flows and standardized high-performance compute silicon (GPUs, x86/ARM CPUs, high-speed networking, and memory architectures).

Skills

Required:Silicon product engineeringProcess node evaluation (sub-2nm, GAA/RibbonFET)Heterogeneous integration (CoWoS, InFO, 3D, HBM)DFM/DFT, yield modeling, test optimizationVendor engagement and technical governance

Benefits

  • Learn more about benefits at Google (provided in job description link)
Last updated Oct 23, 2026. Interested? Apply on the company site.

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