Senior ASIC Physical Design Engineer
Google· AI and Infrastructure
Sunnyvale, CA, USA$163k - $236kFull-timePosted 1w ago
About the role
Senior ASIC Physical Design Engineer to shape AI/ML hardware acceleration and drive TPU technology, collaborating across RTL, DFT, floorplanning, and full-chip signoff to optimize power, performance, and area in complex blocks and full-chip workflows.
Responsibilities
- Participate in the physical design of complex blocks.
- Contribute to the design and closure of the full chip and individual blocks from RTL-to-GDS.
- Collaborate with internal logic and internal and external teams to achieve the best power/performance analysis (PPA). This includes conducting feasibility studies for new microarchitectures as well as optimizing runs for finished RTL.
Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 7 years of experience with physical design (e.g., from RTL to GDSII, including key stages like floorplanning, place and route, and timing closure).
- Experience in Python, Tcl, or Perl scripting.
Skills
Required:Physical design (PD)Scripting (Python, Tcl, Perl)
Nice to have:Static timing analysis (STA)PD tooling (Synopsys/Cadence PnR)DFT knowledgePower/Performance/Area trade-offs (PPA)Collaboration across teams
Benefits
- Learn more about Google benefits at the provided career benefits page.
Last updated Oct 23, 2026. Interested? Apply on the company site.
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