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DFT Engineer

NVIDIA· Engineer, ASIC
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Shanghai, ChinaFull-timePosted 4d ago

About the role

DFT Engineer to join silicon engineering team to validate and debug Design-for-Test features in GPUs and SoCs, collaborating with Design, Test, CAD, and Silicon Engineering teams. Opportunity to learn DFT methodologies and contribute to AI, accelerated computing, and next-generation platforms.

Responsibilities

  • Verify DFT features and test infrastructures, including Scan, MBIST, JTAG, and related functionality.
  • Collaborate with Design, Integration, CAD, and Test Engineering teams to define verification scope and test strategies.
  • Execute verification and validation activities at the IP, subsystem, and full-chip levels.
  • Perform RTL and gate-level debugging to identify and resolve design and test issues.
  • Generate and validate test patterns and support silicon bring-up and debug activities.
  • Improve engineering productivity through scripting, automation, and workflow enhancements.
  • Support verification flow and methodology improvements.

Qualifications

  • 1+ years of experience with an M.S. degree in Electrical Engineering, Electronics Engineering, Microelectronics, IC Design, or closely related discipline.
  • Strong understanding of digital circuits, computer architecture, and semiconductor design fundamentals.
  • Strong analytical, problem-solving, and debugging skills.
  • Familiarity with RTL simulation and debug tools such as Verdi and VCS.
  • Basic understanding of SoC architecture, including clocking, reset, power, and I/O concepts.
  • Programming or scripting experience with Python, Tcl, Perl, C, or C++.
  • Fluent verbal and written communication skills in English.
  • Strong teamwork skills and willingness to learn in a fast-paced environment.

Skills

Required:Design-for-Test (DFT) verificationRTL and gate-level debuggingRTL verification toolsProgramming/scripting

Benefits

  • Not specified in description
Last updated Oct 23, 2026. Interested? Apply on the company site.

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