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ASIC TOP Floorplan Intern, 2027

NVIDIA· Intern
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ShanghaiinternPosted 4d ago

About the role

Intern ASIC TOP Floorplan Design Engineer at NVIDIA focusing on developing and optimizing floorplans for early chip development, collaborating across ASIC design teams to improve area, timing, and routing, and building tooling to enhance chip area and performance.

Responsibilities

  • Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development.
  • Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities.
  • Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.
  • You will build tools and improve existing infrastructure to optimize chip area and speed of execution.

Qualifications

  • Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent work/learning experience.
  • Experience in Verilog, System Verilog or similar HVL.
  • Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.
  • Strong communication and interpersonal skills and ability & desire to work as a great teammate should be displayed in your interview.
  • Python, Perl and C/C++ programming language experience.

Skills

Required:VerilogSystemVerilogCAD and physical design methodologiesFloorplanningPythonPerlC/C++
Last updated Oct 23, 2026. Interested? Apply on the company site.

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