Senior Verification Engineer – High Speed Coherent Interconnect Hub
NVIDIA· Engineer, Verification
Santa Clara, CA$136k - $218.5k + equityFull-timePosted 4d ago
About the role
Senior Verification Engineer to verify High Speed Coherent Interconnect Hub IP within NVIDIA's Tegra SoC IP Verification team. Responsible for verification strategy, environments, functional and performance verification, coverage closure, and collaboration across architecture, design, FPGA/emulation, software, and post-silicon teams.
Responsibilities
- Develop and maintain verification infrastructure, including testbenches, BFMs, checkers, monitors, scoreboards, assertions, and constrained-random stimulus.
- Define, review, and complete verification test plans for coherency protocol, ordering, error handling, performance, and other key IP features.
- Verify protocol compliance and interoperability across complex SoC and multi-chip interfaces.
- Develop and complete performance test plans to validate bandwidth, latency, QoS, and other performance requirements.
- Drive functional and code coverage closure and provide to verification signoff.
- Debug complex RTL and verification issues and work with architecture and design teams to resolve them.
- Collaborate with FPGA, emulation, software, and post-silicon teams to support system validation and silicon bring-up.
Qualifications
- BS / MS or equivalent experience.
- 3+ years of ASIC verification experience with complex IPs or SoC subsystems.
- Strong background in SystemVerilog, UVM, constrained-random verification, and coverage-driven verification methodologies.
- Experience developing verification environments, checkers, assertions, and functional coverage.
- Strong debugging and problem-solving skills with experience using industry-standard simulation and debug tools.
Skills
Required:SystemVerilogUVMconstrained-random verificationfunctional coverage
Benefits
- equity
- benefits package (NVIDIA benefits)
Last updated Oct 23, 2026. Interested? Apply on the company site.
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