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Senior Silicon DFT Micro Architecture Engineer, Google Cloud

Google
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BengaluruFull-timePosted 3d ago

About the role

Be part of a team building DFT solutions for custom silicon powering Google's infrastructure. Design and validate DFT strategies across ASIC development, from circuit to high-volume manufacturing, with impact on data center hardware.

Responsibilities

  • Develop DFT strategy and architecture (e.g., hierarchical DFT, DFT for high-speed I/Os, Analog DFT).
  • Develop and drive die-level DFT validation strategy, complete all Test Design Rule Checks (TDRC), and execute design changes to fix TDRC violations to achieve high test quality.
  • Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, clock control block, and other DFT IP blocks.
  • Document DFT architecture, test sequences, and boot-up sequences associated with test pins.
  • Generate and deliver production and debug patterns to the post-silicon engineering team, and run diagnosis for post-silicon support.

Qualifications

  • Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
  • 8 years of experience in the implementation and validation of DFT technologies.
  • Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion.
  • Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow.
  • Experience in leading DFT activities throughout an ASIC development flow.

Skills

Required:Electrical EngineeringDFT design and verification
Nice to have:IP integration ( memories, test controllers, TAP )
Last updated Oct 23, 2026. Interested? Apply on the company site.

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