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CPU Design for Test Engineer, Google Cloud

Google
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Tel Aviv; HaifaFull-timePosted 4d ago

About the role

DFT engineering role focused on design-for-test solutions for ASICs, developing flows, automation, and methodology to enable tapeout-ready testability of complex devices within Google's AI and Infrastructure teams.

Responsibilities

  • Execute activities in the design, implementation, and verification of Design for Testing solutions for ASICs.
  • Develop DFT strategy for array DFT, hierarchical DFT, Scan, and Automatic Test Pattern Generation (ATPG).
  • Perform ATPG, scan coverage debug and drive design fixes for coverage and quality improvements.
  • Perform DFT verification at RTL and gate level.
  • Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT design requirements are met and mutual dependencies are managed.

Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
  • 4 years of experience with Design For Test (DFT) methodologies, DFT verification, and industry-standard DFT tools.
  • Experience with industry-standard Automatic Test Pattern Generation (ATPG) methods, fault modeling, and scan coverage debug.
  • Experience validating Memory Built-In Self-Test (MBIST) structures and Joint Test Action Group (JTAG)/Test Access Port (TAP) controllers.
  • Experience running structural verification, debugging testbenches, or simulation tracking utilizing simulators.

Skills

Required:Design For Test (DFT) methodologiesATPG methodsMBIST validationJTAG/TAP controllersRTL and gate-level DFT verificationCollaboration with Design/Verification/Physical Design teams
Nice to have:Python or Tcl for EDA flows
Last updated Oct 23, 2026. Interested? Apply on the company site.

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