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Chip Package Signal and Power Integrity Engineer

Google· AI and Infrastructure
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Sunnyvale, CA, USA$163k - $236kFull-timePosted 4d ago

About the role

Lead SI/PI analysis and chip/package design for high-performance computing, focusing on TPU architecture integration and advanced packaging in Google’s AI/ML hardware initiatives.

Responsibilities

  • Lead SI/PI analysis for High-Performance Computing (HPC) utilizing 2.5D/3D package technologies to define specifications and optimize chip floorplans, power trees, and netlists.
  • Drive next-generation memory interface development and evaluate high-speed Interface IPs, balancing complex trade-offs across IO PHY, SI/PI, and physical design.
  • Own post-silicon validation and qualification of high-speed interfaces to ensure successful New Product Introduction (NPI).
  • Partner with chip/system design teams, suppliers, and vendors to establish SI/PI goals, define design boundaries, and manage DFM trade-offs.
  • Provide crucial feedback on chip floorplans to maximize package/system routability and SI/PI, while developing methodologies to improve simulation accuracy and productivity.

Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 7 years of experience with SI/PI design for chip/package or system PCB.
  • Experience in industry Signal integrity and Power Integrity (SIPI) modeling tool chains (e.g., HFSS, ADS, Sigrity, Siwave, etc.).

Skills

Required:SI/PI design2.5D/3D package design
Nice to have:Static Timing Analysis / timing budgetsProgramming / scripting for automation

Benefits

  • Learn more about benefits at Google.
Last updated Oct 23, 2026. Interested? Apply on the company site.

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