Physical Design Lead, Static Timing Analysis
Google· Google Hardware / AI Infrastructure
Sunnyvale, CA$192k - $278kFull-timePosted 3d ago
About the role
Lead timing constraint creation and validation, timing analysis, and ECOs for complex ASICs, driving STA methodology and integration with RTL, DFT, and chip implementation in Google's TPU/AI hardware stack.
Responsibilities
- Lead effort for timing constraint creation and validation, timing analysis and timing Engineering Change Order (ECO) creation, and final timing sign-off for complex ASICs.
- Drive both static timing analysis methodology development and support, as well as chip implementation and timing signoff execution.
- Develop, support and execute implementation flows around industry-standard static timing and parasitic extraction tools.
- Interface with the broader team to triage and resolve reported technical issues, escalating complex tool-related problems to EDA vendors and deliver timely and effective solutions.
- Lead collaboration with RTL design and DFT team for high quality integrations and timing constraints.
Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience in static timing analysis (STA), including 5 years of experience in a technical leadership capacity.
- Experience achieving full-chip timing convergence and authoring, reviewing, or validating timing constraints (e.g., Synopsys Design Constraints (SDC)).
- Experience using tool command language (Tcl) commands for timing analysis, timing closure, parasitic extraction, noise glitch, or crosstalk.
- Experience using electronic design automation (EDA) tools (e.g., PrimeTime, Tempus, Timevision, or STAR-RC).
- Experience analyzing cross-chip clock distribution networks.
Skills
Required:Timing constraint creation and validationStatic timing analysis (STA)EDA tools (PrimeTime, Tempus, Timevision, STAR-RC)Tcl scripting for EDACross-chip clock distribution analysisRTL/DFT collaboration
Benefits
- Learn more about benefits at Google (link provided in job description).
Last updated Oct 23, 2026. Interested? Apply on the company site.
More open roles at Google
- Staff Network Security Engineer, Google Enterprise Network3d agoHybrid (Austin, TX; Sunnyvale, CA)
- Group Product Manager, Google Lens AI Shopping3d agoMountain View, CA, USA · Product Management
- UX Program Manager3d agoHybrid (New York, NY; San Bruno, CA) · UX Programs & Operations
- Senior Staff Software Engineer, Android Automotive OS3d agoHybrid (Kraków, Poland; Munich, Germany)
- 3d ago