Mgr III, ASIC - AMZ25936.5
Amazon· Corporate Operations
Cupertino, CA$223.6k - $272.4kfull-timePosted yesterday
About the role
Lead a verification engineering team for AI-focused SoC designs, defining verification strategies, building UVM-based testbenches, and ensuring coverage for neural network accelerators, high-speed interconnects, and memory subsystems at Annapurna Labs (U.S.) Inc. in Cupertino, CA.
Responsibilities
- Lead a team of verification engineers in the functional verification of advanced AI-focused System-on-Chip (SoC) designs, including neural network accelerators, high-speed interconnects, and memory subsystems.
- Manage project schedules, deliverables, and performance metrics while mentoring and developing junior engineers.
- Define, develop, and implement comprehensive verification strategies and testplans aligned with AI-specific architectural and performance goals.
- Oversee creation of modular, reusable UVM-based testbenches for verifying components such as compute engines, DMA controllers, and AI-specific processing blocks.
- Collaborate closely with architecture, RTL design, software, and machine learning teams to ensure full coverage of functional requirements and performance metrics.
- Drive verification closure through coverage-driven verification methodologies, including code, functional, and assertion coverage.
- Utilize simulation tools, formal verification techniques, and emulation platforms to validate complex AI workloads and edge-case scenarios.
Qualifications
- A Master’s degree or foreign equivalent in Computer Science, Computer Engineering or related field and 5 year(s) of experience in the job offered or a related occupation. In the alternative, a Bachelor’s degree or foreign equivalent in Computer Science, Computer Engineering or related field followed by 8 year(s) of progressively responsible experience in the job offered or a related occupation.
- Must have 5 year(s) of experience in the following: Design verification using System Verilog and UVM. Testbench development including: testplans, stimulus, checkers, assertions and coverage. Verify and integrate multiple levels of design including: custom chip blocks, 3rd party IPs and VIPs, sub-systems, and fullchip SOC systems.
Skills
Required:SystemVerilogUVM (Universal Verification Methodology)Testbench development
Benefits
- base pay range: $223,641 - $272,400 per year ( Cupertino, CA )
- sign-on bonus and restricted stock units may be provided
- medical, financial, and/or other benefits, dependent on the position offered
Last updated Oct 25, 2026. Interested? Apply on the company site.
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