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Sr. Manager, Foundation IP (Standard Cells & Memories)

Amazon· Annapurna Labs
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Cupertino, CA$277.4k - $350kfull-timePosted 2d ago

About the role

Lead the Foundation IP organization responsible for standard cells, memories and related IP in AWS MLA silicon efforts (Trainium/Inferentia). Own end-to-end foundation IP strategy, vendor relationships, PPA optimization, and team leadership across DTCO, cell/memory definition, characterization, and silicon correlation on advanced nodes.

Responsibilities

  • Foundation IP strategy & vendor ownership — own the foundation IP roadmap (standard cell libraries, memory compilers, custom macros, GPIO/ESD, eFuse/OTP, PVT sensors) aligned to Trainium/Inferentia product plans.
  • Serve as the primary technical interface to foundation IP vendors and the foundry: define deliverable specifications, negotiate SOWs and schedules, drive ECOs, version control and release cadence.
  • Influence vendor roadmaps to secure differentiating features and PPA; resolve quality escapes with data.
  • Build IP intake and QA mechanisms — checklists, regressions and acceptance criteria for every library, memory and view drop.
  • Memory specification & vendor interface — define memory requirements for ML accelerator workloads and integration support for PD/DFT teams.
  • Latch arrays & custom memory macros — design and integrate latch-based arrays and custom register files; drive selection methodology and PPA benefit quantification.
  • Custom & combo standard cells — identify opportunities, write specifications, and drive topology, sizing, pin access, routability and DFM; lead through characterization and PnR enablement.
  • Characterization & signoff views — own PVT strategy, signoff flows and model/EM/thermal qualification; drive SPICE correlation.
  • Foundry DTCO & node enablement — engage with foundry on DTCO, device options and silicon characterization plans for N3/N2 and below.
  • Team leadership — hire, develop and lead a small team; report IP health, risks and PPA metrics to senior leadership.

Qualifications

  • 3+ years of people management, managing engineers
  • BS in Electrical or Computer Engineering with 12+ years, MS with 10+ years, or PhD with 7+ years in standard cell, memory or custom digital circuit design
  • Hands-on transistor-level design experience across standard cells, sequentials/latches, and SRAM or register files in FinFET or GAA technologies at 5nm or below
  • Experience as the technical interface to foundation IP vendors or foundries — specifying deliverables and driving SOWs, schedules, ECOs and IP quality
  • Experience evaluating standard cell library and memory PPA using block-level synthesis and place-and-route
  • Experience with standard cell and memory characterization and EDA views (Liberty/LVF, LEF, Verilog) using Synopsys PrimeLib/SiliconSmart or Cadence Liberate
  • Proficiency with custom design and verification tools: Cadence Virtuoso or Synopsys Custom Compiler; Spectre or HSPICE/PrimeSim; Siemens Calibre or Synopsys ICV
  • Scripting experience in Python, Tcl, Perl or SKILL

Skills

Required:Foundation IP strategy & vendor ownershipPPA evaluation & library selectionMemory specification & vendor interfaceCharacterization & signoffFoundry DTCO & node enablementTeam leadership
Nice to have:Latch arrays & custom memory macrosCustom & combo standard cells

Benefits

  • Health insurance (medical, dental, vision, prescription)
  • Basic Life & AD&D insurance and optional Supplemental life plans
  • EAP, Mental Health Support, Medical Advice Line
  • Flexible Spending Accounts
  • Adoption and Surrogacy Reimbursement coverage
  • 401(k) matching
  • Paid time off
  • Parental leave
Last updated Oct 25, 2026. Interested? Apply on the company site.

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