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ASIC Physical Design Engineer

Jane Street· Technology
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LondonFull-timePosted 3mo ago

About the role

ASIC Physical Design Engineer with RTL reading/writing experience to design, test, and deploy advanced hardware as part of the Ultra Low Latency team. Role blends physical design leadership with RTL understanding and front-end/back-end awareness, encouraging use of software techniques to improve hardware design processes.

Responsibilities

  • Build and run modern physical design flows (e.g., floorplanning, place and route, timing closure, physical verification, power analysis) end-to-end
  • Own a PD flow end-to-end and identify risks across the PD process
  • Read and write RTL and understand how front-end decisions affect physical implementation (and vice versa)
  • Collaborate across trading, networking and research infrastructure teams
  • Explore and adopt software engineering techniques to improve hardware design workflow
  • Engage with the Hardcaml toolchain and related OCaml-based tooling when applicable

Qualifications

  • 8+ years hands-on experience building and running modern physical design flows (e.g., floorplanning, place and route, timing closure, physical verification, power analysis)
  • Broad PD experience across the flow with ability to own end-to-end processes
  • Ability to read and write RTL and understand cross-boundary design decisions (front-end vs back-end)
  • Experience programming in a high-level language (Python, C++, Haskell, etc.)
  • Fluent in English

Skills

Required:Physical design flowsRTL reading/writingFront-end / back-end design integrationEnglish proficiency
Nice to have:Programming

Benefits

  • Equal Opportunity Employer
Last updated Oct 25, 2026. Interested? Apply on the company site.

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