ASIC Physical Design Engineer
Jane Street· Technology
New York$250k - $300kfull-timePosted 3mo ago
About the role
ASIC Physical Design Engineer on the Ultra Low Latency team, combining PD leadership with RTL reading/writing and cross-front-end/back-end design awareness. Opportunity to own end-to-end PD flow while collaborating with trading, networking, and research infrastructure; familiar with Hardcaml toolchain and potential OCaml-based tooling.
Responsibilities
- Build and run modern physical design flows (e.g., floor planning, place and route, timing closure, physical verification, power analysis)
- Own a PD flow end-to-end
- Read and write RTL and understand how front-end decisions affect physical implementation (and vice versa)
- Collaborate across chip design stack, influencing design decisions beyond PD
- Leverage software engineering techniques to improve hardware design processes
Qualifications
- 8+ years hands-on experience building and running modern physical design flows (e.g., floor planning, place and route, timing closure, physical verification, power analysis)
- Broad PD experience to own a flow end-to-end and identify risks
- Ability to read and write RTL and understand cross-boundary design impacts between front-end and physical implementation
- Experience programming in a high-level language (Python, C++, Haskell, etc.)
- comfort with tools and willingness to adopt new tooling (Hardcaml)
- Experience across RTL design and PD, or working on smaller teams with multiple hats
Skills
Required:Physical DesignRTL Reading/WritingLanguages
Nice to have:Software Engineering for HW
Benefits
- Base salary of $250,000 - $300,000
- Annual discretionary bonus as part of total compensation
- Equal Opportunity Employer
Last updated Oct 25, 2026. Interested? Apply on the company site.
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