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Principal Silicon Design Verification Engineer

Microsoft· Silicon Engineering
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Santa Clara, CA, Mountain View, CA, Hillsboro, OR, Austin, TX, Redmond, WA$142.8k - $274.8kfull-timePosted 4mo ago

About the role

Microsoft SCHIE (Silicon, Cloud Hardware, and Infrastructure Engineering) enables Microsoft’s cloud infrastructure. The role focuses on validating silicon for a Data Processing Unit (DPU) in datacenter environments, with cross-functional collaboration and opportunities for growth.

Responsibilities

  • As a Principal Engineer in the Data Processing Unit team, you will be validating silicon to solve complex problems in a datacenter.
  • Lead key components of functional validation of complex ASIC SOC using UVM/C test bench
  • Perform pre-silicon SoC verification, post-silicon validation by defining testing strategies
  • Work with cross functional teams, architecture, design, verification, partner teams for project execution and influence next generation designs
  • Develop test plan, C tests and infrastructure to complete functional validation of complex design and report bug/issues
  • Running tests, debugging failures, creating stress and performance scenarios to meet test plan goals
  • Actively participate in chip bring up and write test firmware to support various teams
  • Innovate to improve validation efficiency through methodologies and tools
  • Coach and mentor others in your areas of expertise
  • Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion

Qualifications

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.

Skills

Required:UVM/C verification methodology
Nice to have:VerilogSystemVerilogtestbench developmentpre-silicon validation
Last updated Oct 23, 2026. Interested? Apply on the company site.

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