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Principal Silicon Engineer

Microsoft· Silicon Engineering
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Indiafull-timePosted 3mo ago

About the role

Microsoft SCHIE Data Processing Unit (DPU) team seeks a Static Timing Analysis (STA) experienced engineer to drive STA execution from early design exploration to signoff for high-performance ASICs, focusing on timing closure, methodology, and cross-team collaboration across project phases.

Responsibilities

  • Take ownership and responsibility for our STA execution
  • Develop, improve, and update our STA methodology; work closely with vendors to align our flows to industry practices, resolve tool issues, and improve overall execution and reliability of STA flows
  • Take an active role in early-phase design planning with STA execution including full-chip repeater planning, timing budgeting, constraint development, and early analysis
  • Define & drive to STA milestones across project phases; manage STA rollups, analysis & reporting, ECO generation flows, and guidance to block development
  • Ensure a convergent STA process and drive STA closure through all phases including final signoff for tapeout
  • Work across teams to identify and resolve boundary timing issues, fullchip STA bottlenecks, etc. Give guidance for floorplan adjustments and address timing issues, constraints, etc.

Qualifications

  • Bachelor’s degree in computer engineering, electrical engineering, or related field
  • 7+ years of physical design/STA experience
  • Experience with Synopsys design tools (e.g., DC, ICC2/Fusion-Compiler, PrimeTime)

Skills

Required:Static Timing Analysis (STA)
Nice to have:Flow automation and scriptingTiming closure managementTapeout experience
Last updated Sep 10, 2026. Interested? Apply on the company site.

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