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Principal Silicon Engineer

Microsoft· Silicon Engineering
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IndiaFull-timePosted 3mo ago

About the role

Full-chip Integration and DPU silicon team role within Microsoft SCHIE, focusing on C4/package interfaces, chip finishing, RDL optimization, and power delivery for high-performance ASICs in the Data Processing Unit (DPU) team.

Responsibilities

  • Take ownership and responsibility for our fullchip/package integration
  • Take an active role in early-phase design planning with die size planning, floorplanning, C4/microbump development, and RDL insertion & optimization
  • Develop, enhance, and maintain full-chip integration methodologies; collaborate with vendors and partners to align workflows with industry practices, address tool-related issues, and improve the reliability and efficiency of full-chip finishing and integration processes.
  • Define & drive to integration milestones across project phases; manage interaction and integration with package team & vendors to ensure continuity of entire system design
  • Manage multiple power domains & islands, ensuring correctness and robustness of the design
  • Ensure a convergent integration process and drive package closure through all phases including final signoff for tapeout
  • Work across teams to identify and resolve power delivery issues, integration issues, etc; provide guidance for floorplan adjustments to address power integrity issues and continuity of the package and board design

Qualifications

  • Bachelor’s degree in computer engineering, electrical engineering, or related field
  • 7+ years of physical design experience with focus on C4 integration & chip finishing
  • Experience with ASIC design tools (e.g., DC, ICC2/Fusion-Compiler, PrimeTime) & Physical Verification tools (e.g., Calibre)

Skills

Required:C4 integrationRDL optimizationchip finishingpower delivery planningfloorplanning
Nice to have:flow automation / scriptingpackaging interfaces
Last updated Jul 23, 2026. Interested? Apply on the company site.

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