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Member of Technical Staff - Microarchitectural Validation

Architect Labs· ASIC
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Bangalore, IndiaFull-timePosted 3mo ago

About the role

Member of Technical Staff focusing on design verification and validation for AI-generated designs taping out on leading foundries, combining hardware verification with AI-driven design automation.

Responsibilities

  • Review AI-driven test plan, and validation strategy for internal and external SoC projects.
  • Provide domain-specific expertise to AI/ML teams, including architectural and microarchitectural checks, validation modularity, checkers, coverage models, and interface protocols — helping encode DV best practices into AI-driven flows.
  • Independently define, drive, and coordinate validation, verification, and integration flows across multiple IPs, including checkpoints and collateral handoffs.
  • Collaborate with architecture, design, and AI/ML leads to generate simulation- and emulation-ready collateral that scales across projects.
  • Track emerging trends in semiconductor verification and AI-driven design automation to keep methodology cutting-edge in quality, scalability, and throughput.

Qualifications

  • Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
  • 5+ years (10+ preferred) tapeout experience on advanced-node tapeouts at top chip companies or fast-moving silicon startups; end-to-end silicon delivery is a strong plus.
  • Deep expertise in verification/validation, emulation, and architectural and system-level verification of industry-standard IPs; proven track record defining microarchitectural checkers and monitors, modeling IP and SoC validation platforms, and developing modular, reusable validation collateral.
  • Strong skills in SystemVerilog, UVM, and C/C++ for test environments; Python strongly preferred.
  • Hands-on verification experience in at least one of: ARM/AMBA protocols, CPU subsystems, memory controllers and PHY, NoC/On-chip interconnect, NPU/ML accelerator cores, Security IPs.
  • Experience with simulation and emulation flows, and methodologies; experience mapping IP and SoC designs to FPGA prototypes for fast functional verification.
  • Excellent problem-solving, collaboration, and communication skills; ability to work independently and drive cross-functional alignment.
  • Leadership ability to lead the DV function over time as the team scales.

Skills

Required:Electrical Engineering / Computer Engineering degreeTapeout experienceVerification/validation / emulation expertiseSystemVerilog, UVM, C/C++Subsystem verification areasSimulation and emulation methodologies
Nice to have:Leadership in DV

Benefits

  • Competitive salary and meaningful equity stake
  • Fast-paced startup with autonomy and visible impact
  • Cutting-edge challenges at the intersection of AI and silicon design
Last updated Sep 27, 2026. Interested? Apply on the company site.

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Architect Labs

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