Member of Technical Staff - Formal Verification
Architect Labs· ASIC
Palo AltoFull-timePosted 2mo ago
About the role
Formal verification engineer responsible for AI-generated chip design artifacts from specifications to tape-out, developing formal verification plans, environments, and proofs to ensure correct hardware behavior.
Responsibilities
- Develop and execute formal verification plans using AI for hardware blocks and subsystems. Identify critical properties, define the scope of verification, and establish clear criteria for closure.
- Work with the AI researchers to build Spec to SVA flows including test plans, formal testbenches that capture functional requirements, interface protocols, and corner cases. Review assumptions against the specification and the environment the block will operate in.
- Drive proofs to completion using abstraction, decomposition, invariants, and appropriate solver strategies. Diagnose inconclusive results and make difficult designs tractable without hiding the behavior you need to verify.
- Debug counterexamples, isolate root causes, and work with RTL designers to resolve issues. Turn bugs into regression properties that catch the same failure in future revisions.
- Assess verification completeness through coverage analysis, reachability checks, vacuity checks, and assumption reviews. Document what has been proven, what remains open, and where simulation or other methods are needed.
- Build reusable verification components and automate formal regressions, result tracking, and failure triage. Work with our formal methods and ML teams to bring these checks into the AI-driven design flow.
Qualifications
- Degree: BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- RTL and Assertions: Strong SystemVerilog and SVA skills. Ability to read complex RTL, understand microarchitecture, and write properties that capture intended behavior.
- Formal Tools: Hands-on experience with Cadence Jasper, Synopsys VC Formal, or Siemens Questa Formal. Build verification environments, debug failed proofs, and improve proof convergence.
- Proof Techniques: Practical understanding of model checking, induction, abstraction, and assume-guarantee reasoning. Understand constraints and modeling choices impact on proofs.
- Hardware Understanding: Comfortable reasoning about control logic, pipelines, arbitration, buffering, and interface protocols, including reset behavior, backpressure, and concurrent transactions.
- Engineering Rigor: Strong scripting skills in Python, Tcl, or similar languages. Create repeatable workflows and ensure verification results traceable to requirements and design revisions.
- Ownership: Capable of working from incomplete specifications, resolving ambiguity with designers, and making clear technical judgments under tape-out deadlines.
Skills
Required:SystemVerilogFormal verification toolsProof techniquesPython/Tcl scriptingHardware fundamentalsOwnership and communication
Benefits
- Competitive salary and meaningful equity stake
- Fast-paced startup with autonomy and visible impact
- A foundational role at the intersection of formal verification, AI, and silicon
Last updated Sep 27, 2026. Interested? Apply on the company site.
About Architect Labs
Architect Labs
Architect is a frontier AI lab for chip design.
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