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Microarchitect / RTL Design - Interconnect & Fabric

Architect Labs· Architecture
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Palo AltoFull-timePosted 2mo ago

About the role

Architect Labs is seeking a Technical Staff member to own AI-driven microarchitecture and RTL design of on-chip interconnect fabric and high-speed I/O data movement subsystems for production silicon, including NoC routers, crossbar switches, fabric bridges, and peer-to-peer data transfer engines.

Responsibilities

  • Own the on-chip fabric RTL end-to-end: from NoC topology and router microarchitecture through code generation, lint, CDC, synthesis, and timing closure using our AI-driven design flow.
  • Design and implement AMBA-based interconnect fabrics: AXI/ACE/CHI-compliant crossbar switches, network interfaces (NIs), protocol converters (AXI-to-CHI bridges, AXI-to-AHB/APB downconverters), and multi-layer interconnect configurations optimized for ML accelerator traffic patterns.
  • Architect NoC routers and topologies: virtual-channel routers, wormhole/flit-based switching, adaptive routing algorithms, QoS-aware arbitration (bandwidth regulation, latency-critical path prioritization), and deadlock-free network design for mesh/ring/tree topologies.
  • Design high-speed I/O fabric bridges and peer-to-peer engines: PCIe/CXL-to-fabric bridges, chip-to-chip interconnect logic (UCIe, custom die-to-die links), peer-to-peer DMA controllers for direct device-to-device transfers bypassing host memory, and coherent/non-coherent multi-chip fabric extensions.
  • Work directly with the principal architect to refine microarchitectural specs, resolve implementation trade-offs, and feed area/timing/power realities back into the architecture and internal AI systems.
  • Define and maintain interface specifications: AMBA AXI4/AXI5, ACE/ACE-Lite, CHI (with snoop filter interfaces), AXI-Stream for streaming datapaths, custom sideband channels for QoS/ordering, and high-speed SerDes-facing interfaces for off-chip links.
  • Build and maintain RTL infrastructure for our in-house AI-driven flow: design automation scripts, NoC configuration generators, regression flows, lint/CDC waivers, and integration collateral for the interconnect subsystem.
  • Close collaboration with DV: support verification bring-up with interconnect reference models, protocol compliance checkers, SVA assertions for ordering rules and deadlock freedom, and architectural documentation for verification closure.
  • Close collaboration with SW and ML: guide SW/ML experts to revise and improve our AI flow based on interconnect domain expertise, particularly around traffic modeling and fabric configuration optimization.
  • Support FPGA prototyping on Xilinx for early functional validation of the fabric, including multi-master traffic generation and performance characterization on FPGA platforms.

Qualifications

  • Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
  • 5+ years (10+ preferred) in RTL design with at least one advanced-node tapeout experience involving on-chip interconnects, NoC fabrics, or high-speed I/O subsystems.
  • Deep familiarity with ARM AMBA protocol suite — AXI4/AXI5, ACE/ACE-Lite, CHI, and legacy AHB/APB.
  • Hands-on experience designing or owning crossbar switches, NoC routers, or multi-layer interconnects including arbitration schemes, virtual channel management, flow control, and QoS mechanisms.
  • Experience with HSIO bridge logic — PCIe root complex/endpoint, CXL protocol translation, or custom die-to-die links (UCIe).
  • Experience with peer-to-peer DMA architectures and direct device-to-device communication paths.
  • SystemVerilog: synthesizable, lint-clean RTL with parameterization and modular fabric composition.
  • SoC Methodology: synthesis, timing constraints, clock domain crossings, reset strategies, and power management for interconnect logic.
  • Python: design automation, traffic generation/analysis, NoC configuration scripting, regression infrastructure.
  • PPA Ownership: experience taking interconnect/fabric blocks RTL through synthesis and working with PD teams on timing/area/power closure.

Skills

Required:RTL designAMBA protocol (AXI4/AXI5, ACE/ACE-Lite, CHI)NoC/fabric designHigh-Speed I/O integrationSystemVerilogPythonSynthesis/timing/constraints
Nice to have:DV/verification collaborationFPGA prototyping (Xilinx)

Benefits

  • (Not explicitly listed in the description)
Last updated Oct 18, 2026. Interested? Apply on the company site.

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