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Microarchitect / RTL Design - Memory Subsystem

Architect Labs· Architecture
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Palo Alto, Bangalore, IndiaFull-timePosted 2mo ago

About the role

RTL design role focused on ownership of the memory subsystem in production silicon, including memory controllers, memory hierarchy, and memory-side accelerators, with AI-driven design flow and collaboration across DV, SW, and ML.

Responsibilities

  • Own the memory subsystem RTL end-to-end: from DDR/HBM controller design through code generation, lint, CDC, synthesis, and timing closure using our AI-driven design flow.
  • Design and implement memory controllers: including DDR5/LPDDR5X PHY-side controller logic, HBM3/HBM3E pseudo-channel controllers, command scheduling, refresh management, and ECC/RAS engines.
  • Architect the memory hierarchy: including multi-level cache controllers, scratchpad memory managers, coherency protocol engines, prefetch engines, and bandwidth partitioning/QoS mechanisms.
  • Design memory-side accelerators: near-memory compute logic, scatter-gather DMA engines, address translation/remapping units, compression/decompression engines co-located with memory interfaces, and intelligent prefetchers tuned for ML access patterns.
  • Work directly with the principal architect to refine microarchitectural specs, resolve trade-offs, and feed area/timing/power realities back into the architecture and internal AI systems.
  • Define and maintain interface specifications: DDR PHY interfaces (DFI), HBM PHY interfaces, on-chip SRAM interfaces, AXI/ACE/CHI for memory-facing fabric ports, and custom interfaces for near-memory accelerator datapaths.
  • Build and maintain RTL infrastructure for our in-house AI-driven flow: design automation scripts, regression flows, lint/CDC waivers, and integration collateral for the memory subsystem.
  • Close collaboration with DV: support verification bring-up with memory timing models, protocol-compliant BFMs, SVA assertions for JEDEC protocol compliance, coverage plans targeting worst-case scheduling scenarios, and architectural documentation for verification closure.
  • Close collaboration with SW and ML: support and guide SW/ML experts to revise and improve our AI flow based on memory subsystem domain expertise.
  • Support FPGA prototyping on Xilinx for early functional validation of memory controllers, including bring-up with DDR MIG IPs and HBM validation platforms.

Qualifications

  • Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
  • 5+ years (10+ preferred) in RTL design with at least one advanced-node tapeout experience involving memory subsystems (DDR/LPDDR/HBM controllers, cache hierarchies, or memory-intensive SoC subsystems).
  • Deep familiarity with JEDEC memory standards — DDR5/LPDDR5X command/address protocols, timing parameters, training sequences, and/or HBM2E/HBM3 pseudo-channel architecture, stack addressing, and interleaving schemes.
  • Hands-on experience designing or owning memory controller blocks including command schedulers, bank state machines, refresh engines, read/write turnaround optimization, and PHY interface timing (DFI or proprietary).
  • Experience with multi-level cache design, scratchpad controllers, or unified memory architectures with partitioning and QoS.
  • SystemVerilog: synthesizable, lint-clean RTL with strong design habits and parameterization for multi-standard support (DDR5/HBM3).
  • Experience with SRAM controllers and arbiters, bank conflict resolution, address hashing/interleaving, ECC encode/decode engines, and high-bandwidth data movement between on-chip and off-chip memory.
  • Solid grasp of synthesis, timing constraints, clock domain crossings, reset strategies, AMBA protocols (AXI/ACE/CHI), and memory subsystem power management.
  • Python: strong skills for design automation, performance modeling, regression infrastructure, and tooling.
  • PPA ownership: experience taking a memory controller or cache subsystem from RTL through synthesis and working with PD teams on timing/area/power closure.

Skills

Required:RTL designMemory subsystem architectureSystemVerilogPythonAMBA protocols (AXI/ACE/CHI)DDR5/LPDDR5X/HBM3 memory techECC/RASRegression/integration tooling
Last updated Sep 27, 2026. Interested? Apply on the company site.

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