Member of Technical Staff - Physical Design
Architect Labs· ASIC
Palo AltoFull-timePosted 1mo ago
About the role
Architect Labs is hiring a Physical Design engineer to build the PD function from scratch and lead tapeout-ready physical design for leading-edge nodes (3nm, 2nm and beyond) in a frontier AI silicon environment.
Responsibilities
- Build the methodology: Establish and qualify the complete netlist-to-GDS flow, including PDKs, libraries, tools, constraints, automation, and reproducible regression infrastructure.
- Own implementation: Drive block and full-chip floorplanning, power planning, placement, clock tree synthesis, routing, and ECOs to meet demanding PPA targets.
- Drive signoff: Define release criteria and close timing, signal integrity, EM/IR, DRC/LVS, and foundry-required physical checks through final GDS delivery.
- Work with AI researchers: Translate PD expertise into automated flows, structured tool feedback, and evaluations. Feed post-route results back into architecture, RTL, and our AI system.
- Lead technical partnerships: Resolve process, library, tool, and signoff challenges directly with foundries, EDA vendors, and IP providers.
- Build the team: Set technical standards, define the PD roadmap and hiring priorities, and mentor future hires while remaining hands-on.
Qualifications
- Tapeout ownership: Multiple production tapeouts, with direct physical implementation and signoff responsibility at 3nm or 2nm and experience leading full-chip closure.
- Methodology development: Track record of building production PD methodology from scratch for advanced nodes, including PDK/library qualification, tool evaluation, and deployment across chip programs.
- Technical depth: Deep expertise in hierarchical implementation, multi-mode multi-corner timing analysis, variation, clocking, congestion, low-power design, extraction, and power integrity.
- EDA expertise: Hands-on mastery of Synopsys Fusion Compiler/ICC2 or Cadence Innovus, plus commercial timing, extraction, power integrity, and physical verification tools.
- Automation: Strong Tcl and Python skills, with experience building maintainable flow scripts, automated checks, regressions, and actionable PPA reporting.
- Technical leadership: Ability to independently establish the flow, debug closure problems, and explain trade-offs to hardware, software, and AI teams.
Skills
Required:Tapeout ownershipPD methodology developmentHierarchical implementation & tight PPAEDA toolsAutomation & scriptingTechnical leadership
Benefits
- Competitive compensation and meaningful equity.
- Autonomy to establish the PD function.
- Opportunity to shape AI-driven silicon design from implementation through tapeout.
Last updated Sep 27, 2026. Interested? Apply on the company site.
About Architect Labs
Architect Labs
Architect is a frontier AI lab for chip design.
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