Senior Design Verification Engineer
Microsoft· Hardware Engineering
Hybrid (Multiple Locations), Redmond, WA, Hillsboro, OR, San Francisco, CA, Austin, TX$119.8k - $234.7kFull-timePosted 2w ago
About the role
Senior Hardware Engineer role focused on building, testing, and deploying networking acceleration (FPGA SmartNICs) for Azure, developing SDN infrastructure, and delivering RTL-to-production solutions in a hyperscale cloud environment.
Responsibilities
- Build scalable constrained random verification environment in system Verilog using prevalent verification methodologies.
- Create comprehensive test plans to address functional scenarios in discussions with the software and hardware design teams.
- Execute the test plan by adding testcases and tracking verification through coverage driven metrices.
- Create and enhance verification environment by adding sequences, constraints, assertions, and functional coverage.
- Scripts to automate and maintain execution of test suits to support continuous integration (CI) and continuous development (CD) flow.
- Apply Agile development methodologies such as hosting code reviews, sprint planning, frequent deployment to cloud, and iterative development of features.
- Handle occasional on-call responsibilities for addressing hardware issues reported by our customers.
Qualifications
- Master's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 3+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 5+ years technical engineering experience OR equivalent experience
Skills
Required:SystemVerilogFunctional coverageAgile
Nice to have:UVM (Universal Verification Methodology)Python
Last updated Oct 9, 2026. Interested? Apply on the company site.
About Microsoft
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