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Principal Design Verification Engineer - Formal

Microsoft· Silicon Engineering
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Raleigh, NC, Austin, TX, Hillsboro, OR, Mountain View, CA$142.8k - $274.8kFull-timePosted 2w ago

About the role

Microsoft SCHIE (Silicon, Cloud Hardware, and Infrastructure Engineering) seeks a Principal Design Verification Engineer - Formal to lead formal verification of Fabric Interconnect architectures, IPs, subsystems, and reusable fabric components, and to define strategies, environments, and signoff criteria within the Verification & Validation team.

Responsibilities

  • Own or lead Formal verification of Fabric Interconnect architectures, IPs, subsystems, and reusable Fabric components from planning through signoff.
  • Partner with architecture, design, and verification teams to define Formal verification strategies, methodologies, test plans, and signoff criteria.
  • Develop and enhance Formal verification environments, assertions, abstraction models, checkers, and reusable verification collateral.
  • Drive root-cause analysis and closure of complex design and verification issues through Formal analysis, simulation, and debug.
  • Improve verification productivity through automation, methodologies, and AI-assisted solutions.
  • Coach and mentor engineers in Formal verification methodologies and best practices.
  • Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion.

Qualifications

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.

Skills

Required:Formal verificationFormal verification strategiesDebug and root-cause analysis
Nice to have:Automation and AI-assisted verificationMentoring/formal verification coachingSystemVerilog/UVMPython
Last updated Oct 9, 2026. Interested? Apply on the company site.

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