Principal Formal Design Verification Engineer
Microsoft· Silicon Engineering
Bangalorefull-timePosted 1w ago
About the role
Microsoft SCHIE seeks a Principal Formal Design Verification Engineer to drive formal verification strategy and execution for complex IP/SOC designs, partnering with architecture, design, and verification teams to deliver high-quality cloud hardware.
Responsibilities
- Own or lead Formal verification of Fabric Interconnect architectures, IPs, subsystems, and reusable Fabric components from planning through signoff.
- Partner with architecture, design, and verification teams to define Formal verification strategies, methodologies, test plans, and signoff criteria.
- Develop and enhance Formal verification environments, assertions, abstraction models, checkers, and reusable verification collateral, while driving convergence and execution to closure
- Drive root-cause analysis and closure of complex design and verification issues through Formal analysis, simulation, and debug.
- Improve verification productivity through automation, methodologies, and AI-assisted solutions.
- Coach and mentor engineers in Formal verification methodologies, debug techniques and best practices.
- Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion.
Qualifications
- 12+ years of relevant technical engineering experience
- Bachelor’s or Master’s degree in electrical, electronics, computer engineering, computer science or related field
- 5+ years of hands-on pre-silicon Formal verification experience at the IP, subsystem, or SoC level
Skills
Required:Formal verification
Nice to have:Fabric Interconnects / CHI / AMBA / PCIe / CXLSystemVerilog / UVM / assertions / coverage-driven verificationPython or scriptingAI-assisted verification tooling
Benefits
- (Not explicitly listed in the description)
Last updated Oct 16, 2026. Interested? Apply on the company site.
About Microsoft
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