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Design Verification Engineer

Microsoft· Silicon Engineering
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Raleigh, NC, Austin, TX$102.1k - $202.2kFull-timePosted 1w ago

About the role

Microsoft SCHIE seeks a Design Verification Engineer to join the Shared and Custom IP & Silicon (SCIPS) team within the Compute Silicon & Manufacturing Engineering (CSME) organization to plan and execute verification for complex IP, develop constrained-random and formal verification environments, and collaborate across architecture, design, verification, and firmware to enable high-quality tape-outs for Microsoft cloud hardware.

Responsibilities

  • Plan the verification of complex design IP interacting with the architecture and design engineers to identify verification test scenarios.
  • Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools
  • Develop tests using UVM or C/C++
  • Analyze and debug test failures with designers to deliver functionally correct design.
  • Identify and write functional coverage for stimulus and corner cases.
  • Close coverage to plug verification holes and meet tape-out requirements.
  • Collaborate with cross-functional teams, including Architecture, Design, Verification and FW to deliver products with key differentiators.
  • Engage in chip bring-up activities and write test firmware to assist other teams.
  • Drive innovation by enhancing validation efficiency through new methodologies and tools.
  • Embody Microsoft’s core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive Results, Influence for Impact, Judgement, and Diversity & Inclusion.

Qualifications

  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience OR equivalent experience.

Skills

Required:SystemVerilogUVMC/C++
Nice to have:Formal verificationSystem-on-Chip verification
Last updated Oct 16, 2026. Interested? Apply on the company site.

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