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Senior Logic Design Engineer

Microsoft· Silicon Engineering
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Hillsboro, OR, Redmond, WA, Mountain View, CA, Austin, TX, Raleigh, NC$119.8k - $234.7kFull-timePosted 4d ago

About the role

Senior Logic Design Engineer role within Microsoft Silicon creating RTL with emphasis on static timing analysis, SDC constraints, and synthesis correlation for Physical Design handoff in cloud hardware development.

Responsibilities

  • Design, develop, and maintain robust timing (SDC) constraints ensuring functional correctness, hierarchical consistency, and tool compatibility while enabling PPA targets
  • Leverage state of the art tools to generate constraints and perform quality assurance for PD and STA consumption
  • Collaborate and support Physical Design, STA, and DFT teams with collaterals from initial RTL handoff to tape out
  • Analyze and debug synthesis results to drive RTL optimization towards achieving PPA targets
  • Automate tasks using scripting for efficiency
  • Utilize AI for gaining efficiency within process and development
  • Continue to grow your micro-architectural knowledge and contribute to unit, sub-system and SOC micro-architecture
  • Development and integration of various functional block RTL
  • Perform design quality checks such as Timing closure, Lint, CDC, Synthesis, Low Power Intent
  • Exercise the functionality of the block by writing basic tests and debug for various features at IP and SoC levels as deemed necessary
  • Delight your customers by providing high-quality functional blocks on schedule and with professional integrity
  • Challenge the status quo with growth mindset
  • Mentor team members and summer interns for a growing team

Qualifications

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
  • OR Masters in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
  • OR Bachelors in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
  • OR equivalent experience

Skills

Required:Timing constraints and SDC generationSynthesis and RTL optimizationScripting (Perl, Tcl, Python)Verilog/SystemVerilog
Nice to have:Front-end tools and lintingClock crossings, UPF, low power
Last updated Oct 23, 2026. Interested? Apply on the company site.

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