Senior Design Verification Engineer
Microsoft· Silicon Engineering
Redmond, WA, Mountain View, CA, Austin, TX$119.8k - $234.7kFull-timePosted 4d ago
About the role
Senior Design Verification Engineer to support pre-silicon verification and post-silicon validation for custom IP components, block/sub-system/system level verification, and silicon bring-up within the SCIPS team under SCHIE/CSME.
Responsibilities
- Establish yourself as an integral member of a pre-silicon verification and post-silicon validation team for the development of custom Intellectual Property (IP) components
- Define pre-Si verification (simulation/emulation/FPGA-testing) and post-Si validation strategies and develop test-plans
- Execute end-to-end verification plans at block, sub-system or system level
- Expertise in UVM based verification methodology including coverage closure
- Basic C, C++ programming understanding to develop C based testbenches
- Silicon validation test planning, silicon bring-up and validation activities
- Collaborate across verification teams on vertical and horizontal reuse of components.
- Interact with Architecture, Design, Firmware/Software, Product Engineering, Program Management and third party vendor teams to ensure pre-and-post-Si testing is comprehensive
- Provide technical leadership through mentorship and teamwork.
- Adopt new AI based tools and agents for efficient execution
Qualifications
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
Skills
Required:UVM based verificationC/C++ programmingtest planning and validation
Last updated Oct 23, 2026. Interested? Apply on the company site.
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