Member of Technical Staff - Microarchitect / RTL Design
Architect Labs· Architecture
Palo Alto, Bangalore, IndiaFull-timePosted 3mo ago
About the role
RTL design-focused role owning AI-driven microarchitecture and RTL for mission-critical SoC blocks, collaborating with principal architect and cross-functional teams to deliver production silicon.
Responsibilities
- Own AI-driven RTL design flow end-to-end (at the frontend): through code generation to incorporating feedback from lint, CDC, synthesis, and timing closure stages for closing the design loop.
- Work directly with the principal architect to refine microarchitectural specs, resolve implementation trade-offs, and feed area/timing/power realities back into the architecture and internal AI systems.
- Define and maintain interface specifications (e.g. AXI, AXI-Stream, or custom-built) for block- and SS-level integration.
- Build and maintain RTL infrastructure for our in-house AI-driven flow: design automation scripts, regression flows, lint/CDC waivers, and integration collateral.
- Close collaboration with DV: Support DV bring-up with reference models, assertions, test-plans, and architectural documentation for verification closure.
- Close collaboration with SW and ML: Support and guide our SW and ML experts to revise and improve our in-house AI flow based on your own experience.
- Support FPGA prototyping on Xilinx for early functional validation.
Qualifications
- Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
- 5+ years (10+ preferred) in RTL design with at least one advanced-node tapeout experience, worked on specialized HW accelerators.
- SystemVerilog: Clear, synthesizable, lint-clean RTL with strong design habits such as parameterization, modularity, reuse and configurability.
- Block-Level Depth: Hands-on experience with block-specific compute datapaths and data movement; such as MAC arrays, vector units, accumulators, on-chip SRAM controllers and arbiters, DMA engines, scratchpad memory management, etc.
- SoC Methodology: Solid grasp of synthesis, timing constraints, clock domain crossings, reset strategies, AMBA protocols (AXI, AHB, APB), power management techniques, etc.
- Python: Strong skills for design automation, regression infrastructure, and tooling.
- PPA Ownership: Experience taking a block from RTL through synthesis and working with PD teams on timing/area/power closure.
- Leadership: Ability to lead RTL design efforts and grow into a team lead over time.
Skills
Required:Electrical Engineering / Computer Engineering degreeRTL designSystemVerilogBlock-level compute datapaths & data movementSoC methodologyPythonPPA ownershipLeadership
Benefits
- Competitive salary and meaningful equity stake
- Fast-paced startup with autonomy and visible impact
- Cutting-edge challenges at the intersection of AI and silicon design
Last updated Sep 27, 2026. Interested? Apply on the company site.
About Architect Labs
Architect Labs
Architect is a frontier AI lab for chip design.
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