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Member of Technical Staff - Microarchitectural Validation

Architect Labs· ASIC
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Palo AltoFull-timePosted 3mo ago

About the role

Member of Technical Staff focused on Design Verification & Validation for AI-driven silicon designs, owning verification strategy and cross-IP validation in collaboration with architecture, design, and AI/ML leads at Architect Labs.

Responsibilities

  • Review AI-driven test plan, and validation strategy for internal and external SoC projects.
  • Provide domain-specific expertise to AI/ML teams, including architectural and microarchitectural checks, validation modularity, checkers, coverage models, and interface protocols — helping encode DV best practices into AI-driven flows.
  • Independently define, drive, and coordinate validation, verification, and integration flows across multiple IPs, including checkpoints and collateral handoffs.
  • Collaborate with architecture, design, and AI/ML leads to generate simulation- and emulation-ready collateral that scales across projects.
  • Track emerging trends in semiconductor verification and AI-driven design automation to keep our methodology cutting-edge in quality, scalability, and throughput.

Qualifications

  • Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
  • 5+ years (10+ preferred) working on advanced-node tapeouts at top chip companies or fast-moving silicon startups. End-to-end silicon delivery is a strong plus.
  • Deep expertise in verification/validation, emulation, and architectural and system-level verification of industry-standard IPs. Proven track record defining microarchitectural checkers and monitors, modeling IP and SoC validation platforms, and developing modular, reusable validation collateral.
  • Strong skills in SystemVerilog, UVM, and C/C++ for test environments. Python strongly preferred.
  • Hands-on verification experience in at least one of: ARM/AMBA protocols (APB, AHB, AXI, ACE), CPU subsystems (boot, interrupts, debug, coherency), Memory controllers/PHY (LPDDR/DDR), On-chip interconnect/NoC, NPU/ML accelerator cores, Security IPs/secure enclaves.
  • Experience with simulation and emulation flows and methodologies. Experience mapping IP and SoC designs to FPGA prototypes for fast functional verification.
  • Excellent problem-solving, collaboration, and communication skills with attention to detail. Ability to work independently and drive cross-functional alignment.
  • Leadership: Ability and desire to lead the DV function over time as the team scales.

Skills

Required:Educational qualificationTapeout experienceVerification & validationProgramming languagesSubsystem domains

Benefits

  • Competitive salary and meaningful equity stake
  • Fast-paced startup with autonomy and visible impact
  • Cutting-edge challenges at the intersection of AI and silicon design
Last updated Sep 27, 2026. Interested? Apply on the company site.

About Architect Labs

Architect Labs

Architect is a frontier AI lab for chip design.

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